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| SMC91C100 advance information feast? fast ethernet controller features dual speed csma/cd engine (10 mbps and built-in transparent arbitration for slave 100 mbps) sequential access architecture compliant with ieee 802.3 100base-t flat mmu architecture with symmetric specification transmit and receive structures and supports 100base-tx, 100base-t4, and queues 10base-t physical interfaces mii (media independent interface) compliant 32 bit wide data path (into packet buffer mac-phy interface (compliant with memory) emerging mii standard interface) support for 32 and 16 bit buses mii management serial interface support for 32, 16 and 8 bit cpu accesses seven wire interface to 10 mbps endec synchronous, asynchronous and burst dma (smc83c694) interface mode options eeprom-based setup 128 kbyte external memory 208 pin qfp package general description the SMC91C100 feast is a high-speed network efficient buffer ut ilization scheme, reducing software controller designed to facilitate the implemetation of tasks and relieving the host cpu from performing fast ethernet adapters and connectivity products. these housekeeping functions. the total memory it contains a dual speed csma/cd engine that size is 128 kbytes (external), equivalent to a total implements the mac portion of the csma/cd chip storage (transmit and receive) of 64 protocol at 10 and 100 mbps and couples it with a outstanding packets. lean and fast data and control path system architecture to ensure data movement with no feast provides a flexible slave interface for easy bottlenecks at 100 mbps. c onnectivity with i ndustry-standard buses. the bus memory management is handled using a unique as asynchronous buses, with different signals being mmu (memory management unit) architecture and used for each one. feast's bus interface s upports a 32-bit wide data path. this i/o mapped synchronous buses like the vesa local bus, as well architecture can sustain back-to-back frame as burst mode dma for eisa environments. transmission and reception for superior data asynchronous bus support for isa is supported throughput and optimal performance. it also even though isa cannot sustain 100 mbps traffic. dynamically allocates buffer memory in an fast ethernet could be adopted for isa- interface unit (biu) can handle synchronous as well
2 table of contents features .......................................................................... 1 general description .............................................................. 1 pin configuration ................................................................. 3 description of pin functions ..................................................... 4 functional description ..........................................................14 data structures and registers .................................................17 board setup information ........................................................59 application considerations ......................................................62 operational description.........................................................69 maximum guaranteed ratings ................................................69 dc electrical characteristics...............................................69 timing diagrams ..................................................................72 300 kennedy drive hauppauge, ny 11788 (516) 435-6000 fax (516) 231-6004 /1. 7;(1 ;7$/ ;7$/ 9'' 0,,6(/ q&6287 1& 7; 9'' 5;b(5 5;b'9 ,26 *1' ,26 ,26 5; &2/ &56 5;' 5;' 5;' 9'' 5;' 7;' 7;' 9'' 7;' 7;' 7;(1 q5:( *1' 5' 5' 5' 5' 1& 5' 5' 5' 9'' 5' 5' 5' 5' *1' 5' 5' 5' *1' (1((3 (('2 $ $ $ $ $ $ $ $ $ $ $ $ ' 9'' ' ' ' ' *1' ' ' ' *1' ' 9'' ' ' ' *1' ' ' 9'' ' ' *1' ' *1' 9'' ' ' *1' ' ' ' ' *1' ' q5'<571 q/'(9 9'' q65'< /&/. &56 &2/ 5;' $9'' 5%,$6 $*1 ' /%. 7;' *1' 5;& 0', 7;& 0'2 q)67(3 $8,6(/ $(1 0&/. 9'' q '$7$& 6 ,175 ,175 ,175 9'' *1' :q5 q&<&/( 5(6(7 q9/%86 *1' 9'' q:5 q5' ,17 $5'< *1' ' ' ' ' *1' ' ' ' 9'' ' q%( q%( q%( q%( $ $ $ 60& & 3lq4)3 ((', ((6. ((&6 5' q5:( 1& 5' 5' 5' 5' 9'' 5' 5' *1' 5' 5' 5' 5' 5' 1& q5:( 9'' 966 5' 5' 5' 5' 5' 5' *1' 9'' 5$ 9'' q5:( 5$ 5$ 5$ 5$ 5$ 5$ 5&9'0$ *1' q$'6 5$ 52( 5$ 5$ 5$ 5$ 5$ 5$ 5$ 3 based nodes on the basis of the aggregate traffic wire endec interface that connects to the benefits. smc83c694 for 10base-t and coax 10 mbps feast is software-compatible with the existing mii (media independent interface) specification draft smc9000 family of products and can use current standard, consisting of 4 bit wide data transfers at smc9000 drivers in 16- and 32-bit intel x86-based the nibble rate. f east also interfaces to the mii environments. serial management protocol. four i/o ports (one two different interfaces are supported on the smc83c694 configuration. network side. the first is a conventional seven ethernet networks. the second interface follows the input and three output pins) are provided for pin configuration 4 description of pin functions pin no. name symbol type description buffer 148-159 address a4-a15 i input. decoded by the SMC91C100 to determine accesses to its registers. 145-147 address a1-a3 i input. used by the SMC91C100 for internal register selection. 193 address aen i input. used as an address qualifier. address enable decoding is only enabled when aen is low. 160-163 nbyte nbe0-nbe3 i input. used during SMC91C100 register enable accesses to determine the width of the access and the register(s) being accessed. nbe0- nbe3 are ignored when ndatacs is low (burst accesses) because 32 bit transfers are assumed. 173-170, data bus d0-d31 i/o24 bidirectional. 32 bit data bus used to access 168-166, the SMC91C100's internal registers. data bus 164,144, has weak internal pullups. supports direct 142-139, connection to the system bus without external 137-135, buffering. for 16 bit systems, only d0-d15 are 133, used. 131-129, 127,126, 124,123, 121,118, 117, 115-112, 110 182 reset reset is i nput. this input is not considered active unless it is active for at least 100ns to filter narrow glitches. 95 naddress nads is input. address strobe. for systems that require strobe address latching, the rising edge of nads indicates the latching moment for a1-a15 and aen. all SMC91C100 internal functions of a1- a15, aen are latched except for nldev decoding. 183 ncycle ncycle i input. this active low signal is used to control SMC91C100 synchronous bus cycles. description of pin functions pin no. name symbol type description buffer 5 184 write/nread w/nr i input. defines the direction of synchronous cycles. write cycles when high, read cycles when low. 181 nvl bus nvlbus ip input. when low the SMC91C100 access synchronous bus interface is configured for vl bus accesses. otherwise the SMC91C100 is configured for eisa dma burst accesses. does not affect the asynchronous bus interface. 105 local bus lclk i input. used to interface synchronous buses. clock maximum frequency is 50 mhz. limited to 8.33 mhz for eisa dma burst mode. 175 asynchron- ardy od16 open drain output. ardy may be used when ous ready interfacing asynchronous buses to extend accesses. its rising (access completion) edge is controlled by the xtal1 clock and therefore asynchronous to the host cpu or bus clock. 106 nsynchron- nsrdy o16 output. this output is used when interfacing ous ready synchronous buses and nvlbus=0 to extend accesses. this signal remains normally inactive, and its falling edge indicates completion. this signal is synchronous to the bus clock lclk. 109 nready nrdyrtn i input. this input is used to complete return synchronous read cycles. in eisa burst mode it is sampled on falling lclk edges, and synchronous cycles are delayed until it is sampled high. 176 interrupt int0-int3 o24 outputs. only one of these interrupts is 187-189 selected to be used; the other three are tri- stated. the selection is determined by the value of int sel1-0 bits in the configuration register. description of pin functions pin no. name symbol type description buffer 6 108 nlocal nldev o16 output. this active low output is asserted device when aen is low and a4-a15 decode to the SMC91C100 address programmed into the high byte of the base address register. nldev is a combinatorial decode of unlatched address and aen signals. 177 nread nrd is input. used in asynchronous bus interfaces. strobe 178 nwrite nwr is input. used in asynchronous bus interfaces. strobe 190 ndata path ndatacs ip input. when ndatacs is low, the data path chip select can be accessed regardless of the values of aen, a1-a15 and the content of the bank select register. ndatacs provides an interface for bursting to and from the SMC91C100 32 bits at a time. 54 eeprom eesk o4 output. 4 sec clock used to shift data in and clock out of the serial eeprom. 55 eeprom eecs o4 output. used for selection and command select framing of the serial eeprom. 52 eeprom eedo o4 output. connected to the di input of the serial data out eeprom. 53 eeprom eedi id i nput. connected to the do output of the serial data in eeprom. 13,15,16 i/o base ios0-ios2 ip input. external switches can be connected to these lines to select between predefined eeprom configurations. 51 enable eneep ip input. enables (when high or open) eeprom smc91c 100 accesses to the serial eeprom. must be grounded if no eeprom is c onnected to the SMC91C100. description of pin functions pin no. name symbol type description buffer 7 42, ram data rd0-rd31 i/o4p bidirectional. carries the local buffer memory 40-38, bus read and write data. reads are always 32 bits 36-33, 59,56, wide. writes are controlled individually at the 49-47, byte level. 45-43, 69-67, 65,64, 62-60, 81-76, 71,70 84,87, ram ra2-ra16 o4 outputs. this bus specifies the buffer ram 88,90, address doubleword being accessed by the 91,96, bus SMC91C100. 99,101, 100,98, 89,92, 103,102, 104 97 nroe o4 output. used to read a doubleword from buffer ram. 31,57, nrwe0- o4 outputs. used to write any byte, word or 73,86 rwe3 dword in ram. 93 nreceive nrcvdma o4 output. this pin is active during SMC91C100 dma write memory cycles of receive packets. 3 crystal 1 xtal1 i an external 25 mhz crystal is connected across 4 crystal 2 xtal2 these pins. if a ttl clock is supplied instead, clk it should be connected to xtal1 and xtal2 should be left open. 5,10, power vdd +5v power supply pins. 23,27, 41,63, 74,83, 85,107, 119,125, 132,143, 165,179, 186,191 description of pin functions pin no. name symbol type description buffer 8 205 analog avdd +5v analog power supply pin. power 14,32, ground gnd ground pins. 46,50, 66,75, 82,94, 111,116, 120,122, 128,134, 138,169, 174,180, 185,200 203 analog agnd analog ground pin. ground 2 transmit txen o4 output. used for 10 mbps endec. this pin enable stays low when miisel is high. 201 transmit txd o4 nrz transmit data output for 10 mbps endec data interface. 208 carrier crs id input. carrier sense from 10 mbps endec sense interface. this pin is ignored when miisel is high. 207 collision col id i nput. co llision detection indication from 10 detection mbps endec interface. this pin is ignored when miisel is high. 206 receive rxd ip nrz receive data input from 10 mbps endec data interface. this pin is ignored when miisel is high. 197 transmit txc ip input. 10 mhz transmit clock used in 10 mbps clock operation. this pin is ignored when miisel is high. 199 receive rxc ip input. 10mhz receive clock recovered by the clock 10 mbps endec. this pin is ignored when miisel is high. 202 loopback lbk o4 output. active when loop bit is set (tcr bit 1). independent of port selection (miisel=x). description of pin functions pin no. name symbol type description buffer 9 1 nlink status nlnk ip input. general purpose input port used to convey link status (ephsr bit 14). independent of port selection (miisel=x). 195 nfullstep nfstep o4 output. non volatile output pin. driven by inverse of fullstep (config bit 10). independent of port selection (mii sel=x). 6 mii select miisel o4 output. non volatile output pin. driven by mii select (config bit 15). high indicates the mii port is selected, low indicates the 10 mbps endec is selected. 194 aui select auisel o4 output. non volatile output pin. driven by aui select (config bit 8). independent of port selection (miisel=x). 30 transmit txen100 o4 output to mii phy. envelope to 100 mbps enable 100 transmission. this pin stays low if miisel is mbps low. 19 carrier 100 crs100 ip input from mii phy. envelope of packet mbps reception used for deferral and backoff purposes. this pin is ignored when miisel is low. 12 receive rx_dv id input from mii phy. envelope of data valid data valid reception. used for receive data framing. this pin is ignored when miisel is low. 18 collision co l100 id input from mii phy. co llision detection i nput. detect 100 this pin is ignored when miisel is low. mbps 25,26, transmit txd0-txd3 o4 outputs. transmit data nibble to mii phy. 28,29 data 9 transmit tx25 ip input. transmit clock input from mii. nibble clock rate clock (25 mhz). this pin is ignored when miisel is low. 17 receive rx25 ip input. receive clock input from mii phy. clock nibble rate clock. this pin is ignored when miisel is low. description of pin functions pin no. name symbol type description buffer 10 20,21, receive rxd0- i inputs. received data nibble from mii phy. 22,24 data rxd3 these pins are ignored when miisel is low. 198 manage- mdi ip mii management data input. ment data input 196 manage- mdo o4 mii management data output. ment data output 192 manage- mclk o4 mii management clock. ment clock 11 receive rx_er id input. indicates a code error detected by phy. error used by the SMC91C100 to discard the packet being received. the error indication reported for this event is the same as a bad crc (receive status word bit 13). this pin is ignored when miisel is low. 204 bias rbias analog a bias resistor is connected between this pin resistor input and ground. nominal value is tbd. 7 nchip ncsout o4 output. chip select provided for mapping of select phy functions into SMC91C100 decoded output space. active on accesses to SMC91C100's eight lower addresses when the bank selected is 7. 11 table 1 - SMC91C100 pin requirements function pin symbols number of pins system address bus a1-a15, aen, nbe0-nbe3 20 system data bus d0-d31 32 system control bus reset, nads, lclk, ardy, nrdyrtn, 17 nsrdy, int0-int3, nldev, nrd, nwr, ndatacs, ncycle, w/nr, nvlbus serial eeprom eedi, eedo, eecs, eesk, eneep, 8 ios0-ios2 ram data bus rd0-rd31 32 ram address bus ra2-ra16 15 ram control bus nroe, nrwe0-nrwe3, rcvdma 6 crystal oscillator xtal1, xtal2 2 power vdd, avdd 19 ground gnd, agnd 21 external endec 10 mbps txen, txd, crs, col, rxd, txc, rxc, 12 lbk, nlnk, nfstep, auisel, miisel physical interface 100 mbps txen100, crs100, col100, rx_dv, 16 rx_er, txd0-txd3, rxd0-rxd3, mdi, mdo, mclk clocks tx25, rx25 2 miscellaneous rbias, ncsout 2 total 204 bus int erface unit ar b i t e r me mo ry man ag ement unit di r e ct me mo ry acce s s me di a acce s s con t r ol serial eeprom rd fifo wr fifo addr es s dat a co nt r ol ram 25 mhz 10 mb inter face 100 mb m edi a independent inter face 12 figure 1 - SMC91C100 feast block diagram addr e s s cont r ol da ta addr e s s cont r ol da ta system bus serial eeprom 1o mbps mi i rd0-31 oe , we ra sram 32kx8 1 2 3 4 SMC91C100 feast smc83c694 10base-t int erface 10base-t 100bas e-t 4 int erface chi p 100base-t4 100base-tx int erface log ic 100base-tx or 13 figure 2 - SMC91C100 feast system diagram 14 functional description description of blocks clock generator block the SMC91C100's clock generator uses a 25 mhz crystal connected to pins xtal1 xtal2 and generates two free running clocks: 1) 50 mhz free running clock - supplied to the dma and the arbiter blocks. 2) 25 mhz free running clock - used to run the eph during reset or when no tx25 is present. other clocks: 3) txclk and rxclk are 10 mhz clock inputs. these clocks are generated by the external endec in 10 mbps mode and are only used by the csma/cd block. 4) tx25 is an input clock. it w ill be the nibble rate of the particular phy connected to the mii (2.5 the arbiter block sequences accesses to packet mhz for a 10 mbps phy, and 25 mhz for a ram requested by the biu and by the dma blocks. 100 mbps phy). biu requests represent pipelined cpu accesses to 5) rx25 - this is the mii nibble rate receive clock csma/cd data movement. the external memory used for sampling received data nibbles and devices used are 25ns 32kx8 sram. the cycle running the receive state machine (2.5 mhz for time for cpu consecutive accesses to the data a 10 mbps phy, and 25 mhz for a 100 mbps path is 80ns/doubleword. this time includes phy). arbitration and csma memory cycles. 6) lclk - bus clock - used by the biu for the arbiter is also responsible for contro lling the synchronous accesses. maximum frequency is nrwe0-nrwe3 lines as a function of the bytes 50 mhz for vl bus mode, and 8.5 mhz for being written. read accesses are always 32 bits eisa slave dma. wide, and the arbiter steers the appropriate byte(s) csma/cd block this is a 16-bit oriented block, with fully- independent transmit and receive logic. the data path in and out of the block consists of two 16-bit wide uni-directional fifos interfacing the dma block. the dma port of the fifo stores 32 bits exploiting the 32-bit data path into memory. the control path consists of a set of registers interfaced to the cpu via the biu. dma block this block accesses packet memory on the csma/cd's behalf, fetching transmit data and storing received data. it interfaces the csma/cd transmit and receive fifos on one side, and the arbiter block on the other. the data path is 32 bits wide. the dma machine is able to support full duplex operation. independent receive and transmit counters are used. transmit and receive cycles are alternated when simultaneous receive and transmit accesses are needed. arbiter block the data register, while dma requests represent to the appropriate lanes as a function of the address. the cpu data path consists of two uni-directional fifos mapped at the data register location. these fifos can be accessed in any 15 combination of bytes, word, or doublewords. the determined by using nsrdy. nsrdy is controlled arbiter will indicate 'not ready' whenever a cycle is by lclk and is synchr onous to the bus. initiated that cannot be satisfied by the present state of the fifo. dir ect 32-bit access to the data path is supporte d the depth of the fifos will accommodate the worst ndatacs, external dma-type of d evices will bypass case arbitration and byte access alignment pattern the biu address decoders and can sequentiall y while still preserving the cpu cycle time when acc ess memory with no cpu intervention . accessing the data register. ndatacs acce sses can be used in the dma burst mmu block the hardware memory management unit is similar to the smc91c90's mmu. it does dynamic memory allocation and queuing of transmit and receive packets, and it determines the value of the transmit and receive interrupts as a function of the queues. two separate interfaces are defined; one for the 10 the page size is still 2k, and with a maximum mbps bit rate interface and one for the mii 100 memory size of 128k the mmu uses 64x6 fifos. mbps and 10 mbps nibble rate interface. the 10 mir and mcr values are interpreted in 512 byte mbps endec interface comprises the signals used units. for interfacing ethernet endecs. the 100 mbps biu block the bus interface unit can handle synchronous as well as asynchronous buses; different signals are used for each one. transparent latches are added on the address path using rising nads for latching. when working with an asynchronous bus like isa, the read and write operations are controlled by the edges of nrd and nwr. ardy is used for notifying the system that it should extend the access cycle. the leading edge of ardy is generated by the leading edge of nrd or nwr while the trailing edge of ardy is controlled by the SMC91C100's internal clock and, therefore, is asynchronous to the bus. in the synchronous vl bus type mode, ncycle interface is supported by the SMC91C100 by and lclk are used for read and write operations. providing the means to drive a tri-statable data completion of the cycle may be output, a clock, and reading an input. timing and by using the ndatacs input. by assertin g mo de (nvlbus=1) or in asynchronous cycles . these cycles must be 32-bit cycles. please refer to t he corresponding timing diagrams for details on these cycles. mac-phy interface block interface follows the mii draft standard for 100 mbps 802.3 networks, and it is based on transferring nibbles between the mac and the phy. for the mii interface, transmit data is clocked out using the tx25 clock input, while receive data is clocked in using rx25. switching between the endec and mii interfaces is controlled by the mii select bit in the configuration register. the miisel pin reflects the value of the bit and may be used to control external multiplexing logic. mii management interface block phy management through the mii management framing for each management command is be generated by the cpu. bus interface arbiter mmu buffer ram csma/cd data bus address bus control eeprom eeprom write data reg read data reg tx fifo tx compl fifo rx fifo dma interface address data transmit receive 16 figure 3 - SMC91C100 internal block diagram with data path serial eeprom interface block this block is responsible for reading the serial eeprom upon hardware reset (or equivalent command) and defining defaults for some key registers. a write operation is also implemented by this block which, under cpu command, will program specific locations in the eeprom. this block is an autonomous state machine, and it controls the SMC91C100's internal data bus during active operation. reserved byte count status word last data byte (if odd) bit0 bit15 ram offset (decimal) 0 2 4 2046 max control byte data area 17 figure 4 - data packet format data structures and registers packet format in buffer memory the packet format in memory is similar for the transmit and receive areas. the first word is reserved for the status word, the next word is used to specify the total number of bytes, and it is followed by the data area. the data area holds the packet itself. transmit packet receive packet status word written by csma upon transmit written by csma upon receive completion (see status register) completion (see rx frame status word) byte count written by cpu written by csma data area written/modified by cpu written by csma control byte written by cpu to control written by csma; also has odd/even data bytes odd/even bit 18 byte count - divided by two, it defines the total the data area contains six bytes of destination number of words, including the status word, address followed by six bytes of source the byte count w ord, the data area and address, followed by a variable length number of the control byte. bytes. on transmit, all bytes are provided by the cpu, including the source address. the the receive byte count always appears as even, the SMC91C100 does not insert its own source oddfrm bit of the receive status word indicates if address. on receive, all bytes are provided by the the low byte of the last word is relevant. csma side. the transmit byte count least significant bit w ill be the 802.3 frame length word (frame type in assumed 0 by the controller regardless of the value ethernet) is not interpreted by the SMC91C100. it is written in memory. treated transparently as data both for transmit and data area - the data area starts at offset 4 of the packet structure, and it can extend for up to control byte - for transmit packets the 2043 bytes. control byte is written by the cpu as: receive operations. x x odd crc 0 0 0 0 odd if set, indicates an odd number of bytes, with crc when set, crc w ill be appended to the the last byte being right before the control frame. this bit has only meaning if the nocrc bit byte. if clear, the number of data bytes is even in the tcr is set. and the byte before the control byte is not transmitted. for receive packets the control byte is written by the controller as: 01 odd 00000 odd if set, indicates an odd number of bytes, with bytes is even and the byte before the control the last byte being right before the control byte should be ignored. byte. if clear, the number of data 19 receive frame status word this word is written at the beginning of each receive frame in memory. it is not available as a register. high byte brod bad odd tool too algn err cast crc frm ng short low byte hash value mult cast 54 3210 algnerr frame had alignment error. when mii toolng frame length was longer than 802.3 sel=1 alignment error is set when badcrc=1 and maximum size (1518 bytes on the cable). an odd number of nibbles were received between sfd and rx_dv going inactive. when mii sel=0 tooshort frame length was shorter than 802.3 alignment error is set when badcrc=1 and the minimum size (64 bytes on the cable). number of bits received between sfd and the crs going inactive is not an octet multiple. hash value provides the hash value used to brodcast receive frame was broadcast. receive routines to speed up the group address badcrc frame had crc error, or rx_er was significant bits of the crc calculated on the asserted during reception. destination address, and maps into the 64 bit oddfrm this bit, when set, indicates that the byte of the multicast table, while bits 2,1,0 determine received frame had an odd number of bytes. the bit within the byte selected. examples of the index the multicast registers. can be used by search. the hash value consists of the six most multicast table. bits 5,4,3 of the hash value select a address mapping: address hash value 5-0 multicast table bit ed 00 00 00 00 00 000 000 mt-0 bit 0 0d 00 00 00 00 00 010 000 mt-2 bit 0 01 00 00 00 00 00 100 111 mt-4 bit 7 2f 00 00 00 00 00 111 111 mt-7 bit 7 multcast receive frame was multicast. if hash packet will pass address filtering regardless of other value corresponds to a multicast table bit that is set, filtering criteria. and the address was a multicast, the 20 i/o space the base i/o space is determined by the ios0-2 last word of the i/o area is shared by all banks and inputs and the eeprom contents. to limit the i/o can be used to change the bank in use. registers space requirements to 16 locations, the registers are are described using the following convention: assigned to different banks. the offset name type symbol high byte bit 15 bit14 bit 13 bit 12 bit 11 bit 10 bit9 bit8 xx xxxxxx low byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xx xxxxxx offset defines the address offset within the some registers (like the interrupt ack., or like iobase where the register can be accessed at, interrupt mask) are functionally described as two provided the bank select has the appropriate value. eight bit registers, in that case the offset of each one the offset specifies the address of the even byte (bits 0-7) or the address of the complete word. regardless of the functional description, all registers the odd byte can be accessed using address (offset + 1). is independently specified. can be accessed as doublewords, words or bytes. the default bit values upon hard reset are highlighted below each register. table 2 - internal i/o space mapping bank0 bank1 bank2 bank3 0 tcr config mmu command mt0-1 2 eph status base pnr/arr mt2-3 4 rcr ia0-1 fifo ports mt4-5 6 counter ia2-3 pointer mt6-7 8 mir ia4-5 data mgmt a mcr general purpose data revision c reserved (0) control interrupt ercv e bank select bank select bank select bank select a special bank (bank7) exists to support the addition of external registers. 21 bank select register offset name type symbol e bank select register read/write bsr high byte0011 0011 0011 0011 low byte bs2 bs1 bs0 xxxx x000 bs2, bs1, bs0 determine the bank presently in a doubleword write to offset ch w ill write the use. this register is always accessible and is bank select register but will not write the used to select the register bank in use. registers ch and dh. the upper byte always reads as 33h and can be bank 7 has no internal registers other than the used to help determine the i/o location of feast. bank select register itself. on valid cycles the bank select register is always and a3=0, ncsout is activated to facilitate accessible regardless of the value of bs0-2. implementation of external registers. note that the bank select register can be note: bank7 does not exist in smc91c9x accessed as a doubleword at offset ch, as a word devices. for backward s/w compatib ility bank7 at offset eh, or as at offset fh, however accesses should be done if the revision control where bank7 is selected (bs0=bs1=bs2=1), register indicates the device is SMC91C100. 22 i/o space - bank0 offset name type symbol 0 transmit control register read/write tcr this register holds bits programmed by the cpu to control some of the protocol transmit options. high eph stp mon_ byte loop sqet csn fduplx nocrc xx0000x0 low byte pad_en forcol loop txena 0xxxx000 eph_loop internal loopback at the eph block. without crc and turns itself o ff. when this bit is serial data is looped back when set. defaults low. clear the transmitter ignores its own carrier. when eph_loop is high, the following transmit defaults low. outputs are forced inactive: txd0-3=0h, txen100=txen=0, txd=1. the following nocrc does not append crc to transmitted external inputs are blocked: crs=crs100=0, frames when set; allows software to insert the col=col100=0, rx_dv=rx_er=0. desired crc. defaults to 0 (crc inserted). stp_sqet stop transmission on sqet error. if pad_en when set, the SMC91C100 w ill pad set, stops and disables transmitter on sqe test transmit frames shorter than 64 bytes with 00. error. does not stop on sqet error and transmits does not pad frames when reset. next frame if clear. defaults low. fduplx when set it enables full duplex co llision by not deferring deliberately. after the operation. this will cause frames to be received if collision this bit is reset automatically. this bit they pass the address filter regardless of the defaults low to normal operation. source for the frame. when clear the node will not receive a frame sourced by itself. loop loopback. general purpose output port mon_csn when set, the SMC91C100 monitors the phy chip in loopback mode. carrier while transmitting. it must see its own carrier by the end of the preamble. if it is not txena transmit enabled when set. transmit is seen, or if carrier is lost during transmission, the disabled if clear. when the bit is cleared, the transmitter aborts the frame SMC91C100 w ill complete the current forcol w hen set, the transmitter will force a used to control the lbk pin. typically used to put transmission before stopping. when stopping due to an error, this bit is automatically cleared. 23 i/o space - bank 0 offset name type symbol 2 eph status register read only ephsr this register stores the status of the last frame transmitted. this register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to the packet. packet interrupt processing should use the copy in memory as the register itself w ill be updated by subsequent packet transmissions. the register can be used for real time values (like txena and link ok). if txena is cleared the register holds the last packet completion status. high rx_ovr lost byte n carr tx unrn link_ok ctr_rol exc_def latcol 0 -nlnk pin 0 0 0 0 0 x low ltx sngl byte mult col tx defr ltx brd sqet 16col mul col tx_suc 00000000 txunrn transmit under run. set if under run occurs, it also clears txena bit in tcr. cleared by setting txena high. this bit should never be exc_def excessive deferral. when set set under normal operation. last/current transmit was deferred for more than link_ok general purpose input port driven by packet sent. nlnk pin inverted. typically used for link test. a transition on the value of this bit generates an lost_carr lost carrier sense. when set, interrupt. indicates that carrier sense was not present at rx_ovrn upon fifo overrun, the receiver enabled. this condition causes txena bit in asserts this bit and clears the fifo. the receiver tcr to be reset. cleared by setting txena bit in stays enabled. after a valid preamble has been tcr. detected on a subsequent frame, rx_ovrn is de-asserted. the rx_ovrn int bit in the latcol late collision detected on last transmit interrupt status register will also be set and stay frame. if set, a late collision was detected (later set until cleared by the cpu. note that receive than 64 byte times into the frame). when overruns could occur only if receive memory detected, the transmitter jams and turns itself off, allocations fail. clearing the txena bit in tcr. cleared by ctr_rol counter roll over. when set, one or more 4-bit counters have reached maximum tx_defr transmit deferred. when set, carrier count (15). cleared by reading the ecr register. was detected during the first 6.4 sec of the inter 1518 * 2 byte times. cleared at the end of every end of preamble. valid only if mon_csn is setting txena in tcr. frame gap. cleared at the end of every packet sent. ltx_brd last transmit frame was a broadcast. 24 set if frame was broadcast. cleared at the start of mulcol multiple collision detected for the last every transmit frame. transmit frame. set when more than one collision sqet signal quality error test. for 10 mbps at the end of the packet being sent. systems, the transmitter opens a 1.6 s window 0.8 s after transmission is completed and the snglcol single collision detected for the last receiver returns inactive. during this window, the transmit frame. set when a co llision is detected. transmitter expects to see the sqet signal from cleared when tx_suc is high at the end of the the transceiver. the absence of this signal is a packet being sent. 'signal quality error' and is reported in this status bit. transmission stops and eph int is set if tx_suc last transmit was successful. set if stp_sqet is in the tcr is also set when sqet transmit completes without a fatal error. this bit is is set. this bit is cleared by setting txena high. cleared by the start of a new frame transmission or the behavior of this bit for 100 mbps is presently when txena is set high. fatal errors are: undefined. 16col 16 collisions reached. set when 16 sqet fail and stp_sqet = 1 collisions are detected for a transmit frame. fifo underrun txena bit in tcr is reset. cleared when txena carrier lost and mon_csn = 1 is set high. late collision ltx_mult last transmit frame was a multicast. set if frame was a multicast. cleared at the start of every transmit frame. was experienced. cleared when tx_suc is high 16 collisions 25 i/o space - bank 0 offset name type symbol 4 receive control register read/write rcr high soft strip byte rst crc filt car 0 0 0 0 rxen 00000000 low rx_ byte abort almul prms 00000000 soft_rst software-activated reset. active rxen enables the receiver when set. if cleared, high. initiated by writing this bit high and completes receiving current frame and then goes terminated by writing the bit low. the idle. defaults low on reset. SMC91C100's configuration is not preserved except for configuration, base, and ia0-5 almul when set, accepts all multicast frames registers. eeprom is not reloaded after (frames in which the first bit of da is '1'). when software reset. clear accepts only the multicast frames that match filt_car filter carrier. when set, filters leading edge of carrier sense for 12 bit times (3 nibble prms promiscuous mode. when set, receives times). otherwise recognizes a receive frame as all frames. does not receive its own transmission soon as carrier sense is active. (does not filter unless it is in full duplex!. rx_dv on mii!) strip_crc when set, it strips the crc on aborted due to length longer than 2044 bytes. received frames. when clear, the crc is stored the frame w ill not be received. the bit is cleared in memory following the packet. defaults low. by reset or by the cpu writing it low. the multicast table setting. defaults low. rx_abort this bit is set if a receive frame was 26 i/o space - bank 0 offset name type symbol 6 counter register read only ecr counts four parameters for mac statistics. when any counter reaches 15 an interrupt is issued. all counters are cleared when reading the register, and do not wrap around beyond 15. high byte number of exc. deferred tx number of deferred tx 0000 0000 low byte multiple collision count single collision count 0000 0000 each 4-bit counter is incremented every time the if a packet experiences deferral, the number of corresponding event, as defined in the eph deferred tx field is incremented by one, even status register bit description, occurs. if the packet experienced multiple deferrals during note that the counters can only increment once its co llision retries. per enqueued transmit packet, never faster; limiting the rate of interrupts that can be generated the counter register facilitates maintaining by the counters. for example, if a packet is statistics in the auto release mode where no successfully transmitted after one collision, the transmit interrupts are generated on successful single collision count field is incremented transmissions. by one. if a packet experiences between two to 16 collisions, the multiple collision count reading the register in the transmit service routine field is incremented by one. will be e nough to maintain statistics. 27 i/o space - bank 0 offset name type symbol 8 memory information register read only mir high byte free memory available (in bytes * 256 * m) 11111111 low byte memory size (in bytes * 256 * m) 11111111 free memory available this register can all memory-related information is represented in be read at any time to determine the amount of 256 * m byte units, where the multiplier m is free memory. the register defaults to the determined by the mcr upper byte. memory size upon reset or upon the reset mmu command. these registers default to ffh, which should be memory size - this register can be read to determine the total memory size. interpreted as 256. 28 i/o space - bank 0 offset name type symbol a memory configuration register lower byte - mcr read/write upper byte - read only high memory size multiplier byte (m) 00110101 low byte memory reserved for transmit (in bytes * 256 * m) 00000000 memory reserved for transmit the value written to the mcr is a reserved programming this value allows the host cpu to memory space in addition to any memory reserve memory to be used later for transmit, currently in use. if the memory allocated for limiting the amount of memory that receive transmit plus the reserved space for transmit is packets can use up. when programmed for zero, required to be constant (rather than grow with the memory allocation between transmit and transmit allocations), the cpu should update the receive is completely dynamic. w hen value of this register after allocating or releasing programmed for a non-zero value, the allocation is memory. dynamic if the free memory exceeds the programmed value, while receive allocation the contents of mir as well as the low byte of requests are denied if the free memory is less or mcr are specified in 256 * m bytes. the equal to the programmed value. this register multiplier m is determined by bits 11, 10, and 9 as defaults to zero upon reset. it is not affected by follows (bits 11, 10 and 9 are read only bits used the reset mmu command. by the software driver to transparently run on different controllers of the smc9000 family): device bit 11 bit10 bit 9 m max memory size SMC91C1000102 256*256*2=128k smc91c900011 256*256*1=64k future0114 256k future1008 512k future 1 0 1 16 1m 29 int sel1 int sel0 pin used 0 0 1 1 0 1 0 1 intr0 intr1 intr2 intr3 i/o space - bank1 offset name type symbol 0 configuration register read/write cr the configuration register holds bits that define the adapter configuration and are not expected to change during run-time. this register is part of the eeprom-saved setup. high mii full aui byte select step select no wait 1xx0x000 low byte 1 0 reserved int sel1 int sel0 1011000x mii select used to select the network interface aui select this bit is a general purpose output port. when set, the SMC91C100 w ill use its mii port. its value drives pin auisel and it is typically port and interface a phy device at the nibble rate. connected to mode1 pin of the smc83c694c. when clear, the SMC91C100 w ill use its 10 mbps it can be used to select aui vs. 10 base-t, or as endec interface. this bit drives the mii sel pin. a general purpose non-volatile configuration pin. switching between ports should be done with defaults low. transmitter and receiver disabled and no transmit/receive packets in progress. int sel1-0 used to select one out of four no wait when set, does not request additional tristated. wait states. an exception to this are accesses to the data register if not ready for a transfer. when clear, negates iochrdy for two to three clocks on any cycle to the SMC91C100. full step this bit is a general purpose output port. its inverse value drives pin nfstep and it is typically connected to sel pin of the smc83c694c. it can be used to select the signaling mode for the aui, or as a general purpose non-volatile configuration pin. defaults low. interrupt pins. the three unused interrupts are 30 i/o space - bank1 offset name type symbol 2 base address register read/write bar this register holds the i/o address decode option chosen for the SMC91C100. it is part of the eeprom saved setup, and is not usually modified during run-time. high byte a15 a14 a13 a9 a8 a7 a6 a5 00011000 low byte reserved 0000000x a15-a13 and a9-a5 these bits are compared therefore, the unspecified address lines a4, a10, against the i/o address on the bus to determine a11 and a12 must be all zeros. the iobase for the SMC91C100's registers. the 64k i/o space is fully decoded by the all bits in this register are loaded from the serial SMC91C100 down to a 16 location space, eeprom. the i/o base decode defaults to 300h (namely, the high byte defaults to 18h). 31 i/o space - bank1 offset name type symbol 4 through 9 individual address registers read/write iar these registers are loaded starting at word location 20h of the eeprom upon hardware reset or eeprom reload. the registers can be modified by the software driver, but a store operation w ill not modify the eeprom individual address contents. bit 0 of individual address 0 register corresponds to the first bit of the address on the cable. high byte address 0 00000000 low byte address 1 00000000 high byte address 2 00000000 low byte address 3 00000000 high byte address 4 00000000 low byte address 5 00000000 32 i/o space - bank1 offset name type symbol a general purpose register read/write gpr high byte high data byte 00000000 low byte low data byte 00000000 this register can be used as a way of storing and eeprom, that is normally protected from retrieving non-volatile information in the eeprom accidental store operations. to be used by the software driver. the storage is word oriented, and the eeprom word address to this register w ill be used for eeprom read and be read or written is specified using the six lowest write only when the eeprom select bit in the bits of the pointer register. control register is set. this allows generic this register can also be used to sequentially affect the basic setup of the SMC91C100. program the individual address area of the eeprom read and write routines that do not 33 i/o space - bank1 offset name type symbol c control register read/write ctr high auto byte release 0 rcv_bad 0 0 000x0xx0 low le cr te eeprom byte enable enable enable select reload store 000xx000 rcv_bad when set, bad crc packets are cr enable counter roll over enable. when received. when clear bad crc packets do not set it enables the ctr_rol bit as one of the generate interrupts and their memory is released. interrupts merged into the eph int bit. defaults auto release when set, transmit pages are released by transmit completion if the transmission te enable transmit error enable. when set it was successful (when tx_suc is set). in that enables transmit error as one of the interrupts case there is no status word associated with its merged into the eph int bit. defaults low packet number, and successful packet numbers (disabled). transmit error is any condition that are not even written into the tx completion clears txena with tx_suc staying low as fifo. a sequence of transmit packets will only described in the ephsr register. generate an interrupt when the sequence is completely transmitted (tx empty int will be eeprom select this bit allows the cpu to set), or when a packet in the sequence specify which registers the eeprom reload or experiences a fatal error (tx int will be set). store refers to. w hen high, the general upon a fatal error txena is cleared and the purpose register is the only register read or transmission sequence stops. the packet number written. when low, reload reads configuration, that failed is the present in the fifo ports base and individual address, and store writes register, and its pages are not released, allowing the configuration and base registers. the cpu to restart the sequence after corrective action is taken. reload w hen set, it will read the eeprom and le enable link error enable. when set it upon completing the operation. enables the link_ok bit transition as one of the interrupts merged into the eph int bit. defaults store when set, stores the contents of all low (disabled). writing this bit also serves as the relevant registers in the serial eeprom. clears acknowledge by clearing previous link interrupt upon completing the operation. conditions. low (disabled). update relevant registers with its contents. clears 34 note: when an eeprom access is in progress the internal registers. the cpu can resume the store and reload bits will be read back accesses to the smc91c 100 after both bits are as high. the remaining 14 bits of this register low. a worst case reload operation initiated by will be invalid. during this time attempted r eset or by software takes less than 750sec. read/write operations, other than polling the eeprom status, w ill not have any effect on 35 i/o space - bank2 offset name type symbol 0 mmu command register write only mmucr busy bit readable this register is used by the cpu to control the memory allocation, de-allocation, tx fifo and rx fifo control. the three command bits determine the command issued as described below: high byte low byte command 0 0 n2 n1 n0/busy xyz 0 command set xyz 000 0) noop - no operation 001 1) allocate memory for tx - n2,n1,n0 defines the amount of memory requested as (value + 1) * 256 bytes. namely n2,n1,n0 = 1 w ill request 2 * 256 = 512 bytes. a shift-based divide by 256 of the packet length yields the appropriate value to be used as n2,n1,n0. immediately generates a completion code at the allocation result register. can optionally generate an interrupt on successful completion. n2,n1,n0 are ignored by the SMC91C100 but should be implemented in the SMC91C100's software drivers for smc9000 compatib ility. 010 2) reset mmu to initial state - frees all memory allocations, clears relevant interrupts, resets packet fifo pointers. 011 3) remove frame from top of rx fifo - to be issued after cpu has completed processing of present receive frame. this command removes the receive packet number from the rx fifo and brings the next receive frame (if any) to the rx area (output of rx fifo). 100 4) remove and release top of rx fifo - like 3) but also releases all memory used by the packet presently at the rx fifo output. 36 101 5) release specific packet - frees all pages allocated to the packet specified in the packet number register. should not be used for frames pending transmission. typically used to remove transmitted frames, after reading their completion status. can be used following 3) to release receive packet memory in a more flexible way than 4). 110 6) enqueue packet number into tx fifo - this is the normal method of transmitting a packet just loaded into ram. the packet number to be enqueued is taken from the packet number register. 111 7) reset tx fifos - this command w ill reset both tx fifos--thetx fifo holding the packet numbers awaiting transmission and the tx completion fifo. this command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. the reset tx fifos command should only be used when the transmitter is disabled. unlike the reset mmu command, the reset tx fifos does not release any memory. note 1: bits n2,n1,n0 bits are ignored by the SMC91C100 but should be used for command 0) to preserve software compatibility with the smc91c92 and future devices. they s hould be zero for all other commands. note 2: when using the reset tx fifos command, the cpu is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. packet numbers in the completion fifo can be read via the fifo ports register before issuing the command. note 3: mmu commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number has memory allocated to it. command sequencing a second allocate command (command 1) should not be issued until the present one has completed. completion is determined by reading the failed bit of the allocation result register or through the allocation interrupt. a second release command (commands 4, 5) should not be issued if the previous one is still being processed. the busy bit indicates that a release command is in progress. after issuing command 5, the contents of the pnr should not be changed until busy goes low. after issuing command 4, command 3 should not be issued until busy goes low. busy bit readable at bit 0 of the mmu command register address. when set indicates that mmu is still processing a release command. when clear, mmu has already completed last release command. busy and failed bits are set upon the tra iling edge of command. 37 i/o space - bank2 offset name type symbol 2 packet number register read/write pnr packet number at tx area 00000000 packet number at tx area - the value stored in this register as the packet number written into this register determines which packet parameter. this register is cleared by a reset or number is accessible through the tx area. some a reset mmu command. mmu commands use the number offset name type symbol 3 allocation result register read only arr this register is updated upon an allocate memory mmu command. failed allocated packet number 10000000 failed a zero indicates a successful allocation allocated packet number packet completion. if the allocation fails the bit is set and number associated with the last memory allocation only cleared when the pending allocation is request. the value is only valid if the failed bit is satisfied. defaults high upon reset and reset clear. mmu command. for polling purposes, the alloc_int in the interrupt status register note: for software compatibility with future should be used because it is synchronized to the versions, the value read from the arr after an read operation. sequence: allocation request is intended to be written into the 1) allocate command failed = 0). 2) poll alloc_int bit until set 3) read allocation result register pnr as is, without masking higher bits (provided 38 i/o space - bank2 offset name type symbol 4 fifo ports register read only fifo this register provides access to the read ports of the receive fifo and the transmit completion fifo. the packet numbers to be processed by the interrupt service routines are read from this register. high byte rempty rx fifo packet number 10000000 low byte tempty tx done packet number 10000000 rempty no receive packets queued in the rx tx done packet number packet number fifo. for polling purposes, uses the rcv_int presently at the output of the tx completion bit in the interrupt status register. fifo. only valid if tempty is clear. the packet top of rx fifo packet number packet issued. number presently at the output of the rx fifo. only valid if rempty is clear. the packet is note: for software compatibility with future removed from the rx fifo using mmu versions, the value read from each fifo register is commands 3) or 4). intended to be written into the pnr as is, without tempty no transmit packets in completion rempty = 0 respectively). queue. for polling purposes, uses the tx_int bit in the interrupt status register. is removed when a tx int acknowledge is masking higher bits (provided tempty and 39 i/o space - bank2 offset name type symbol 6 pointer register read/write ptr not empty is a read only bit high auto not byte incr. empty rcv read eten pointer high 00000000 low byte pointer low 00000000 pointer register the value of this register the pointer register should not be loaded until determines the address to be accessed within the the cpu has verified that the not empty bit is transmit or receive areas. it will auto-increment on clear to ensure that the data register fifo is accesses to the data register when auto incr. empty. on reads, if iochrdy is not connected to is set. the increment is by one for every byte the host, the data register should not be read access, by two for every word access, and by four before 370ns after the pointer was loaded to allow for every double word access. when rcv is set, the data register fifo to f ill. the address refers to the receive area and uses the output of rx fifo as the packet number, if the pointer is loaded using 8 bit writes, the low when rcv is clear the address refers to the byte should be loaded first and the high byte last. transmit area and uses the packet number at the packet number register. eten when set, enables early transmit read determines the type of access to follow. if the read bit is high, the operation intended is a not empty when set, indicates that the write read. if the read bit is low, the operation is a data fifo is not empty yet. the cpu can verify write. loading a new pointer value, with the that the fifo is empty before loading a new read bit high, generates a pre-fetch into the data pointer value. this is a read only bit. register for read purposes. readback of the pointer will indicate the value of be loaded with an even value. the address last accessed by the cpu (rather than the last pre-fetched). this allows any interrupt routine that uses the pointer, to save it and restore it without affecting the process being interrupted. underrun detection. normal operation when clear. note: if auto incr. is not set, the pointer must 40 i/o space - bank2 offset name type symbol 8 through bh data register read/write data 8 data 9 data a data b data data register used to read or write the data data high registers. the order to and from the buffer byte/word presently addressed by the fifo is preserved. byte, word and dword pointer register. accesses can be mixed on the fly in any order. this register is mapped into two uni-directional this register is mapped into two consecutive word fifos that allow moving words to and from the locations to facilitate double word move operations SMC91C100 regardless of whether the pointer regardless of the actual bus width (16 or 32 bits). address is even, odd or dword aligned. data goes the data register is accessible at any address in through the write fifo into memory, and is pre- the 8 through ah range, while the number of bytes fetched from memory into the read fifo. if byte being transferred are determined by a1 and accesses are used, the appropriate (next) byte nbe0-nbe3. the fifos are 12 bytes each. can be accessed through the data low or 41 i/o space - bank2 offset name type symbol c interrupt status register read only ist ercv int eph int empty tx int rcv int rx_ovrn alloc int int tx int x0000100 offset name type symbol c interrupt acknowledge register write only ack ercv int empty tx int rx_ovrn int tx int offset name type symbol d interrupt mask register read/write msk ercv int eph int empty tx int rcv int rx_ovrn alloc int int tx int x0000000 this register can be read and written as a word or stays set until acknowledged by writing the as two individual bytes. interrupt acknowledge register with the interrupt mask register bits enable the appropriate bits when high and disable them when eph int set when the ethernet protocol handler low. an enabled bit being set will cause a section indicates one out of various possible hardware interrupt. special conditions. this bit merges exception type ercv int early receive interrupt. set whenever critical to the execution speed of the low level a receive packet is being received, and the drivers. the exact nature of the interrupt can be number of bytes received into memory exceeds obtained from the eph status register (ephsr), the value programmed as ercv threshold and enabling of these sources can be done via (bank 3, offset ch). ercv int the control register. the ercv int bit set. of interrupt sources, whose service time is not 42 the possible sources are: real time reading of the fifo empty is desired, the link - link test transition ctr_rol - statistics counter roll over the tx empty int enable should only be set txena cleared - a fatal transmit error after the following steps: occurred forcing txena to be cleared. tx_suc will be low and the specific reason a) a packet is e nqueued for transmission will be reflected by the bits: b) the previous empty c ondition is cleared txunrn - transmit underrun sqet - sqe error tx int set when at least one packet lost carr - lost carrier transmission was completed. the first packet latcol - late collision number to be serviced can be read from the fifo 16col - 16 collisions ports register. the tx int bit is always the rx_ovrn int set when the receiver overruns ports register. after servicing a packet number, due to a failed memory allocation. the its tx int interrupt is removed by writing the rx_ovrn bit of the ephsr will also be set, but if interrupt acknowledge register with the tx int a new packet is received it will be cleared. the bit set. rx_ovrn int bit, however, latches the overrun condition for the purpose of being polled or rcv int set when a receive interrupt is generating an interrupt, and will only be cleared by generated. the first packet number to be serviced writing the acknowledge register with the can be read from the fifo ports register. the rx_ovrn int bit set. rcv int bit is always the logic complement of the alloc int set when an mmu request for tx pages allocation is completed. this bit is the note: if the driver uses auto release mode it complement of the failed bit in the should enable tx empty int as well as tx int. allocation result register. the alloc tx empty int will be set when the complete int enable bit should only be set following an sequence of packets is transmitted. tx int w ill be allocation command, and cleared upon servicing set if the sequence stops due to a fatal error on the interrupt. any of the packets in the sequence. tx empty int set if the tx fifo goes empty, note: for edge triggered systems, the interrupt can be used to generate a single interrupt at the service routine should clear the interrupt mask end of a sequence of packets enqueued for register, and only enable the appropriate transmission. this bit latches the empty condition, interrupts after the interrupt source is serviced and the bit will stay set until it is specifically cleared (acknowledged). by writing the acknowledge register with the tx empty int bit set. if a bit should be first cleared and then read. (acknowledged) logic complement of the tempty bit in the fifo rempty bit in the fifo ports register. 5 4 3 2 1 0 5 4 3 2 1 0 interrupt status register inte rrupt mask register oe oe rdist 16 data bus d0-7 d8-15 edge detector on link err lemask ctr-rol crmask temask txena tx_svc ephsr interrupts merged into eph int d2 d4 d s q q tx fifo empty wrack d s q q rx_ovrn (ephsr) allocation fa i l ed tx completion fifo not empty rcv fifo not empty rcv int tx int tx empty int alloc int rx_ovrn int eph int int main interrupts ercv int 6 6 43 figure 5 - interrupt structure 44 i/o space - bank 3 offset name type symbol 0 through 7 multicast table read/write mt low byte multicast table 0 00000000 high byte multicast table 1 00000000 low byte multicast table 2 00000000 high byte multicast table 3 00000000 low byte multicast table 4 00000000 high byte multicast table 5 00000000 low byte multicast table 6 00000000 high byte multicast table 7 00000000 45 the 64 bit multicast table is used for group if the almul bit in the rcr register is set, all address filtering. the hash value is defined as the multicast addresses are received regardless of the six most significant bits of the crc of the multicast table values. destination addresses. the three msb's determine the register to be used (mt0-7), while hashing is only a partial group addressing filtering the other three determine the bit within the scheme, but being the hash value available as part register. of the receive status word, the receive routine can if the appropriate bit in the table is set, the packet proper memory structure, the search is limited to is received. comparing only the multicast addresses that have reduce the search time significantly. with the the actual hash value in question. 46 i/o space - bank3 offset name type symbol 8 management interface read/write mgmt high byte 00110011 low byte mdoe mclk mdi mdo 001100mdi pin0 mdoe mii management output enable. when mdi mii management input. the value of the high pin mdo is driven, when low pin mdo is tri- mdi pin is readable using this bit. stated. mclk mii management clock. the value of this bit drives the mdo pin. bit drives the mdclk pin. mdo mii management output. the value of this the purpose of this interface, along with the corresponding pins, is to implement mii phy management in software. 47 i/o space - bank3 offset name type symbol a revision register read only rev high byte 0011 0011 low byte chip rev 0111 0000 chip chip id. can be used by software drivers rev revision id. incremented for each revision to identify the device used. of a given device. chip id value device 3 smc91c90/smc91c92 7 SMC91C100 offset name type symbol c early rcv register read/write ercv high byte 00110011 low rcv byte discrd ercv threshold 00011111 rcv discrd set to discard a packet being whenever the number of bytes written in memory received. for the presently received packet exceeds the ercv threshold threshold for ercv interrupt status register is set. interrupt. specified in 64 byte multiples. ercv threshold, ercv int bit of the 48 i/o space - bank 7 offset name type symbol 0 through 7 external registers ncsout is driven low by the SMC91C100 when a valid access to the external register range occurs. high byte external r/w register low byte external r/w register cycle ncsout SMC91C100 data bus aen=0 driven low. transparently ignored on writes. a3=0 latched on nads rising tri-stated on reads. a4-15 matches i/o base edge. bank select = 7 bank select = 4,5,6 high ignore cycle. otherwise high normal SMC91C100 cycle. 49 typical flow of events for transmit s/w driver mac side 1 issue allocate memory for tx - n bytes - the mmu attempts to allocate n bytes of ram. 2 wait for successful completion code - poll until the alloc int bit is set or enable its mask bit and wait for the interrupt. the tx packet number is now at the allocation result register. 3 load transmit data - copy the tx packet number into the packet number register. write the pointer register, then use a block move operation from the upper layer transmit queue into the data register. 4 issue "enqueue packet number to tx fifo" - this command writes the number present in the packet number register into the tx fifo. the transmission is now enqueued. no further cpu intervention is needed until a transmit interrupt is generated. 5 the enqueued packet w ill be transferred to the mac block as a function of txena (n tcr) bit and of the deferral process state. 6 upon transmit completion the first word in memory is written with the status word. the packet number is moved from the tx fifo into the tx completion fifo. interrupt is generated by the tx completion fifo being not empty. 7 service interrupt - read interrupt status register. if it is a transmit interrupt, read the tx done packet number from the fifo ports register. write the packet number into the packet number register. the corresponding status word is now readable from memory. if status word shows successful transmission, issue release packet number command to free up the memory used by this packet. remove packet number from completion fifo by writing tx int acknowledge register. 50 typical flow of events for receive s/w driver mac side 1 enable reception - by setting the rxen bit. 2 a packet is received with matching address. memory is requested from mmu. a packet number is assigned to it. additional memory is requested if more pages are needed. 3 the internal dma logic generates sequential addresses and writes the receive words into memory. the mmu does the sequential to physical address translation. if overrun, packet is dropped and memory is released. 4 when the end of packet is detected, the status word is placed at the beginning of the receive packet in memory. byte count is placed at the second word. if the crc checks correctly the packet number is written into the rx fifo. the rx fifo being not empty causes rcv int (interrupt) to be set. if crc is incorrect the packet memory is released and no interrupt will occur. 5 service interrupt - read the interrupt status register and determine if rcv int is set. the next receive packet is at receive area. (its packet number can be read from the fifo ports register). the software driver can process the packet by accessing the rx area, and can move it out to system memory if desired. when processing is complete the cpu issues the remove and release from top of rx command to have the mmu free up the used memory and packet number. ,65 6dyh%dqn6hohfw $gguhvv 3wu5hjlvwhuv 0dvn60& &,qwhuuxswv 5hdg,qwhuuxsw5hjlvwhu &doo7;,175ru7;(037< ,175 7;,175" *hw1h[w7; 5;,175" $//2&$7( ,vvxh$oorfdwh0hpru\ &rppdqgwr008 5hdg,qwhuuxsw6wdwxv5hjlvwhu (qtxhxh3dfnhw 6hw5hdg\iru3dfnhw)odj 5hwxuq &rs\5hpdlqlqj7;'dwd 3dfnhwlqwr5$0 5hwxuq%xiihuvwr8sshu/d\hu :ulwh$oorfdwhg3dfnhwlqwr 3dfnhw5hjlvwhu :ulwh$gguhvv3rlqwhu 5hjlvwhu &rs\3duwri7;'dwd3dfnhw lqwr5$0 :ulwh6rxufh$gguhvvlqwr 3urshu/rfdwlrq 6wruh'dwd%xiihu3rlqwhu &ohdu5hdg\iru3dfnhw)odj (qdeoh$oorfdwlrq,qw huuxsw $oorfdwlrq 3dvvhg" 57 SMC91C100 is virtually queuing the packet process has st opped and therefore the fifo w ill not numbers and their status words. be emptied. in this case, the transmit interrupt service routine this mode has the advantage of a smaller cpu can find the next packet number to be serviced by overhead, and faster memory de-allocation. note reading the tx done packet number at the that when auto release=1 the cpu is not fifo ports register. this eliminates the need for provided with the packet numbers that completed the driver to keep a list of packet numbers being successfully. transmitted. the numbers are queued by the SMC91C100 and provided back to the cpu as their note: the pointer register is shared by any process transmission completes. accessing the SMC91C100 memory. in order to 2) one interrupt per sequence of packets: enable process is responsible for reading the pointer value tx empty int and tx int, set auto before modifying it, saving it, and restoring it before release=1. tx empty int is generated only returning from the interrupt. after transmitting the last packet in the fifo. tx int will be set on a fatal transmit error allowing pointer: the cpu to know that the transmit allow processes to be interruptable, the interrupting typically there would be three processes using the 1) transmit loading (sometimes interrupt driven) 2) receive unloading (interrupt driven) 3) transmit status reading (interrupt driven). 1) and 3) also share the usage of the packet number register. therefore saving and restoring the pnr is also required from interrupt service routines. tx fifo tx completion fifo rx fifo csma/cd logical address packet # mmu physical address ram cpu address csma address rx packet number rx fifo packet number packet number register pa c k # o u t m.s. bit only 'empty' 'not empty' tx done packet number 'not empty' interrupt status register rcv int tx empty int tx int alloc int two options 58 figure 11 - interrupt generation for transmit, receive, mmu 59 register eeprom word address configuration register base register ios value * 4 (ios value * 4) + 1 board setup information the following parameters are obtained from the eeprom as board setup information: ethernet individual address i/o base address 10base-t or aui interface mii or endec interface interrupt line selection all the above mentioned values are read from the individual address 20-22 hex eeprom upon hardware reset. except for the individual address, the value of the ios if ios2-0 = 7 , only the individual address is switches determines the offset within the eeprom read from the eeprom. currently assigned values for these parameters, in such a way that many are assumed for the other registers. these values identical boards can be plugged into the same are default if the eeprom read operation follows system by just changing the ios jumpers. hardware reset. in order to support a software ut ility based the eeprom select bit is used to determine the installation, even if the eeprom was never type of eeprom operation: a) normal or b) general programmed, the eeprom can be written using purpose register. the SMC91C100. one of the ios combination is associated with a fixed default value for the key a) normal eeprom operation - eeprom parameters (i/o base, interrupt) that can select bit = 0 always be used regardless of the eeprom based value being programmed. this value will be used if on eeprom read operations (after reset or after all ios pins are left open or pulled high. setting reload high) the configuration the eeprom is arranged as a 64 x 16 array. the with the eeprom values at locations defined by the specific target device is the 9346 1024-bit serial ios2-0 pins. the individual address registers eeprom. all eeprom accesses are done in are updated with the values stored in the words. all eeprom addresses in the spec are individual address area of the eeprom. specified as word addresses. register and base register are updated 60 on eeprom write operations (after setting the purpose register is written at the eeprom store bit) the values of the configuration word address defined by the pointer register register and base register are written in 6 least significant bits. the eeprom locations defined by the ios2-0 pins. the three least significant bits of the control read and write operations respectively. polling the register (eeprom select, reload and value until read low is used to determine completion. store) are used to control the eeprom. their w hen an eeprom access is in progress the values are not stored nor loaded from the store and reload bits of ctr will readback as eeprom. both bits high. no other bits of feast can be read b) general purpose register - eeprom and both bits are clear. this mechanism is also select bit = 1 valid for reset initiated reloads. on eeprom read operations (after setting note: if no eeprom is connected to the reload high) the eeprom word address defined smc91c 900, for example for some embedded by the pointer register 6 least significant bits applications, the eneep pin should be grounded is read into the general purpose register. and no accesses to the eeprom will be attempted. on eeprom write operations (after setting the their default values upon hardware reset and the store bit) the value of the general cpu is responsible for programming them for their reload and store are set by the user to initiate or written until the eeprom operation completes configuration, base, and individual address assume final value. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. ia0-1 ia2-3 ia4-5 ios2-0 word address 000 0h 1h 4h 5h 8h 9h ch dh 10h 11h 14h 15h 18h 19h 20h 21h 22h 001 010 011 100 101 110 xxx 16 bits 61 figure 12 - 64 x 16 serial eeprom map 62 application considerations the SMC91C100 is envisioned to fit a few different e) 100 mbps mii compliant phy bus types. this section describes the basic f) some bus specific glue logic guidelines, system level implications and sample configurations for the most relevant bus types. all target systems: applications are based on buffered architectures with a private sram bus. a) vl local bus 32 bit systems fast ethernet slave adapter slave non-inte lligent board implementing 100 mbps and 10 mbps speeds. adapter requires: systems, the SMC91C100 is accessed as a 32 bit a) SMC91C100 fast ethernet controller except the data register w ill be accessed b) four srams (32k x 8 - 25ns) using byte or word instructions. accesses to the c) serial eeprom (93c46) data register could use byte, word, or dword d) 10 mbps endec and transceiver chip instructions. b) high-end isa machines c) eisa 32 bit slave vl local bus 32 bit systems on vl local bus and other 32 bit embedded peripheral in terms of the bus interface. all registers table 3 - vl local bus signal connections vl 0 signal notes bus signa l smc91c10 a2-a15 a2-a15 address bus used for i/o space and register decoding, latched by nads rising edge, and transparent on nads low time m/nio aen qualifies valid i/o decoding - enabled access when low. this signal is latched by nads rising edge and transparent on nads low time w/nr w/nr direction of access. sampled by the SMC91C100 on first rising clock that has ncycle active. high on writes, low on reads. nrdyr nrdyrtn ready return. direct connection to vl bus. tn nlrdy nsrdy nsrdy has the appropriate functionality and timing to create the vl nlrdy and some except that nlrdy behaves like an open drain output most of the time. logic lclk lclk local bus clock. rising edges used for synchronous bus interface transactions. nrese reset connected via inverter to the SMC91C100. t table 3 - vl local bus signal connections vl 0 signal notes bus signa l smc91c10 63 nbe0 nbe0 nbe1 byte enables. latched transparently by nads rising edge. nbe1 nbe2 nbe3 nbe2 nbe3 nads nads, address strobe is connected directly to the vl bus. ncycle is created typically ncycle by using nads delayed by one lclk. irqn intr0- typically uses the interrupt lines on the isa edge connector of vl bus. intr3 d0-d31 d0-d31 32 bit data bus. the bus byte(s) used to access the device are a function of nbe0-nbe3: b be1 nbe be3 e 2 0 0 0 0 0 double word access 0011low word access 1 1 0 0 high word access 0111byte 0 access 1011byte 1 access 1101byte 2 access 1110byte 3 access n not used = tri-state on reads, ignored on writes. note that nbe2 and nbe3 override the value of a1, which is tied low in this application. nldev nldev nldev is a totem pole output. nldev is active on valid decodes of a15-a4 and aen=0. unused pins vcc nrd, nwr gnd a1, nvlbus open ndatacs 64 high-end isa machines on isa machines, the SMC91C100 is accessed as peripheral) is provided. the signal connections are a 16 bit peripheral. no support for xt (8 bit listed in the following table: table 4 - high-end isa machines signal connections isa bus SMC91C100 signal signal notes a1-a15 a1-a15 address bus used for i/o space and register decoding aen aen qualifies valid i/o decoding - enabled access when low niord nrd i/o read strobe - asynchronous read accesses. address is valid before leading edge niowr nwr i/o write strobe - asynchronous write access. address is valid before leading edge. data is latched on trailing edge iochrdy ardy this signal is negated on leading nrd, nwr if necessary. it is then asserted on clk rising edge after the access condition is satisfied. reset reset a0 nbe0 nsbhe nbe1 irqn intr0-intr3 d0-d15 d0-d15 16 bit data bus. the bus byte(s) used to access the device are a function of nbe0 and nbe1: nbe0 nbe1 d0-d7 d8-d15 0 0 lower upper 0 1 lower not used 1 0 not used upper not used = tri-state on reads, ignored on writes. niocs16 nldev buffered nldev is a totem pole output. must be buffered using an open collector driver. nldev is active on valid decodes of a15-a4 and aen=0. table 4 - high-end isa machines signal connections isa bus SMC91C100 signal signal notes 65 unused pins vcc nbe2, nbe3, no upper word access. ncycle, w/nr nrdyrtn gnd lclk, nads open d16-d31, ndatacs, nvlbus 66 eisa 32 bit slave on eisa, the SMC91C100 is accessed as a 32 bit smc91c 100 accepts burst transfers, and is able to i/o slave, along with a slave dma type "c" data sustain the peak rate of one doubleword every path option. as an i/o slave, the SMC91C100 uses bclk. doubleword alignment is assumed for dma asynchronous accesses. in creating nrd and nwr transfers. up to 3 extra bytes in the beginning and at inputs, the timing information is externally derived the end of the transfer should be moved by the cpu from ncmd edges. given that the access will be at using i/o accesses to the data register. the least 1.5 to 2 clocks (more than 180ns at least) SMC91C100 w ill sample exrdy and post pone there is no need to negate exrdy, simplifying the dma cycles if the memory cycle solicits wait states. eisa interface implementation. as a dma slave, the table 5 - eisa 32 bit slave signal connections eisa bus SMC91C100 signal signal notes la2-15 a2-a15 address bus used for i/o space and register decoding, latched by nads (nstart) trailing edge. m/nio aen qualifies valid i/o decoding - enabled access when low. aen these signals are externally ored. internally the aen pin is latched by nads rising edge and transparent while nads is low. latched w-r nrd i/o read strobe - asynchronous read accesses. address is combined with valid before its leading edge. must not be active during dma ncmd bursts if dma is supported. latched w-r nwr i/o write strobe - asynchronous write access. address is combined with valid before leading edge. data latched on trailing edge. ncmd must not be active during dma bursts if dma is supported. nstart nads address strobe is connected to eisa nstart. resdrv reset nbe0, nbe1, nbe0, nbe1, byte enables. latched on nads rising edge. nbe2, nbe3 nbe2, nbe3 irqn intr0-intr3 interrupts used as active high edge triggered. table 5 - eisa 32 bit slave signal connections eisa bus SMC91C100 signal signal notes 67 d0-d31 d0-d31 32 bit data bus. the bus byte(s) used to access the device are a function of nbe0-nbe3: nbe nbe nbe nbe 0123 0 0 0 0 double word access 0011low word access 1 1 0 0 high word access 0111byte 0 access 1011byte 1 access 1101byte 2 access 1 1 1 0 byte 3 access not used = tri-state on reads, ignored on writes. note that nbe2 and nbe3 override the value of a1, which is tied low in this application. other combinations of nbe are not supported by the smc91c 100. s/w drivers are not anticipated to generate them. nex32 nldev nldev is a totem pole output. nldev is active on valid nnows decodes of the SMC91C100's pins a15-a4 and aen=0. (optional nnows is similar to nldev except that it should go inactive additional logic) on nstart rising. nnows can be used to request compressed cycles (1.5 bclk long, nrd/nwr w ill be 1/2 bclk wide). the following signals support slave dma type "c" burst cycles bclk lclk eisa bus clock. data transfer clock for dma bursts. ndak table 5 - eisa 32 bit slave signal connections eisa bus SMC91C100 signal signal notes 68 unused pins vcc nvlbus gnd a1 open 69 operational description maximum guaranteed ratings* operating temperature range ................................................ 0 ( c to +70 ( c storage temperature range ...............................................-55 ( c to +150 ( c lead temperature range (soldering, 10 seconds) ..................................... +325 ( c positive voltage on any pin, with respect to ground .................................. v + 0.3v cc negative voltage on any pin, with respect to ground ..................................... -0.3v maximum v ..................................................................... +7v cc *stresses above those listed above could cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. note: when powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is s uggested that a clamp circuit be used. dc electrical characteristics (t = 0 ( c - 70 ( c, v = +5.0 v 10%) acc parameter symbol min typ max units comments i type input buffer low input level high input level v 0.8 v ttl levels ili v2.0 v ihi is type input buffer low input level high input level schmitt trigger hysteresis v 0.8 v schmitt trigger ilis v 2.2 v schmitt trigger ihis v 250 mv hys i input buffer clk low input level high input level v0.4v ilck v3.0 v ihck input leakage (all i and is buffers except pins with pullups/pulldowns) low input leakage high input leakage i-10 +10 ) av = 0 il i-10 +10 ) av = v ih in in cc parameter symbol min typ max units comments 70 ip type buffers input current i -150 -75 ) av = 0 il in id type buffers input current i +75 +150 ) av = v ih in cc o4 type buffer low output level high output level output leakage v 0.4 v i = 4 ma ol v 2.4 v i = -2 ma oh i-10 +10 ) a v = 0 to v ol ol oh in cc i/o4 type buffer low output level high output level output leakage v 0.4 v i = 4 ma ol v 2.4 v i = -2 ma oh i-10 +10 ) a v = 0 to v ol ol oh in cc o12 type buffer low output level high output level output leakage v 0.5 v i = 12 ma ol v 2.4 v i = -6 ma oh i-10 +10 ) a v = 0 to v ol ol oh in cc o16 type buffer low output level high output level output leakage v 0.5 v i = 16 ma ol v 2.4 v i = -8 ma oh i-10 +10 ) a v = 0 to v ol ol oh in cc od16 type buffer low output level output leakage v 0.5 v i = 16 ma ol i-10 +10 ) a v = 0 to v ol ol in cc parameter symbol min typ max units comments 71 o24 type buffer low output level high output level output leakage v 0.5 v i = 24 ma ol v 2.4 v i = -12 ma oh i-10 +10 ) a v = 0 to v ol ol oh in cc i/o24 type buffer low output level high output level output leakage v 0.5 v i = 24 ma ol v 2.4 v i = -12 ma oh i-10 +10 ) a v = 0 to v ol ol oh in cc supply current active i 60 95 ma all outputs open. supply current standby i 8 ma cc csby capacitance t = 25 ( c; fc = 1mhz; v = 5v acc parameter symbol unit test condition limits min typ max clock input capacitance c 20 pf all pins except pin in under test tied to ac ground input capacitance c 10 pf in output capacitance c 20 pf out capacitive load on outputs nardy, d0-d31 (non vlbus) 240 pf d0-d31 in vlbus 45 pf all other outputs 45 pf w w w w w w$ $$(1q%(q%(ydolg ''ydolg $''5(66 q$'6 5($''$7$ q5'q:5 :5,7('$7$ 72 figure 13 - asynchronous cycle - nads = 0 timing diagrams parameter min typ max units t1 a1-a15, aen, nbe0-nbe3 valid and nads low setup 25 ns to nrd, nwr active t2 a1-a15, aen, nbe0-nbe3 hold after nrd, nwr 20 ns inactive (assuming nads tied low) t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns w w w w w w w$ $$$(1q%(q%(ydolg ''ydolg $''5(66 q$'6 5($''$7$ q5'q:5 :5 , 7 ( '$7$ 73 figure 14 - asynchronous cycle - using nads parameter min typ max units t1 a1-a15, aen, nbe0-nbe3 valid and nads low setup 25 ns to nrd, nwr active t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns w w w w w w$ ''ydolg q '$7$& 6 q$'6 5($''$7$ q5'q:5 :5 , 7 ( '$7$ 74 figure 15 - asynchronous cycle - nads = 0 (ndatacs used to select data register; must be 32 bit access) parameter min typ max units t1 a1-a15, aen, nbe0-nbe3 valid and nads low setup 25 ns to nrd, nwr active t2 a1-a15, aen, nbe0-nbe3 hold after nrd, nwr 20 ns inactive (assuming nads tied low) t3 nrd low to valid data 40 ns t4 nrd high to data floating 30 ns t5 data setup to nwr inactive 30 ns t5a data hold after nwr inactive 5 ns w w w w w w w w de f /&/. q '$7$& 6 :q5 q&<&/( :5,7('$7$ q5'<571 75 figure 16 - burst write cycles - nvlbus = 1 parameter min typ max units t12 ndatacs setup to either ncycle or w /nr falling 60 ns t13 ndatacs hold after either ncycle or w/nr rising 30 ns t14 nrdyrtn setup to lclk falling 15 ns t15 nrdyrtn hold after lclk falling 2 ns t17 ncycle high and w/nr high overlap 50 ns t18 data setup to lclk rising (write) 13 ns t20 data hold from lclk rising (write) 5 ns w w w w w w w f de /&/. q'$7$&6 :q5 5($''$7$ q5'<571 q&<&/( 76 figure 17 - burst read cycles - nvlbus = 1 parameter min typ max units t12 ndatacs setup to either ncycle or w /nr falling 60 ns t13 ndatacs hold after either ncycle or w/nr rising 30 ns t14 nrdyrtn setup to lclk falling 15 ns t15 nrdyrtn hold after lclk falling 2 ns t17 ncycle high and w/nr high overlap 50 ns t19 data delay from lclk rising (read) 5 38 ns w w w a1-15,aen,nbe0-nbe3 q$'6 $''5(66 q/'(9 77 figure 18 - address latching for all modes parameter min typ max units t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t25 a4-a15, aen to nldev delay 20 ns w w w w w$ w w w w w ''ydolg $$(1q%(q%( /&/. :q5 $''5(66 q$'6 q&<&/( :5 , 7 ( '$7$ q65'< q '$7$& 6 78 figure 19 - synchronous write cycle - nvlbus = 0 parameter min typ max units t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t10 ncycle setup to lclk rising 7 ns t11 ncycle hold after lclk rising (non-burst mode) 3 ns t16 w/nr setup to ncycle active 30 ns t17a w/nr hold after lclk rising with nlrdy active 5 ns t18 data setup to lclk rising (write) 13 ns t20 data hold from lclk rising (write) 5 ns t21 nlrdy delay from lclk rising 10 ns w w w w w w w w w w ''ydolg $$(1q%(q%( /&/. :q5 $''5(66 q$'6 q&<&/( 5($''$7$ q65'< 5'<571 q'$7$&6 79 figure 20 - synchronous read cycle - nvlbus = 0 parameter min typ max units t8 a1-a15, aen, nbe0-nbe3 setup to nads rising 10 ns t9 a1-a15, aen, nbe0-nbe3 hold after nads rising 15 ns t10 ncycle setup to lclk rising 7 ns t11 ncycle hold after lclk rising (non-burst mode) 3 ns t16 w/nr setup to ncycle active 30 ns t20 data hold from lclk rising (write) 5 ns t21 nlrdy delay from lclk rising 10 ns t23 nrdyrtn setup to lclk rising 7 ns t24 nrdyrtn hold after lclk rising 3 ns w w w w w :5,7(&<&/( 5($'&<&/( gdwdrxw gdwdlq 5$5$ 5q:(q5:( q52( 5'5' 80 figure 21 - sram interface parameter min typ max units t34 ra2-ra16nn setup to nrwe-0-nrwe3 fa lling 0 ns t35 ra2-ra16nn hold after nrwe-0-nrwe3, nroe 0 ns rising t36 write - rd0-rd31 setup to nrwe0-nrwe3 rising 12 ns t37 write - rd0-rd31 hold after nrwe0-nrwe3 rising 0 ns t38 read - ra2-ra16 valid to rd0-rd31 valid 25 ns w w w w w 7;& 7;(1 7;' 5;' 5;& &56 81 figure 22 - endec interface - 10 mbps parameter min typ max units t30 txd, txen delay from txc rising 0 40 ns t31 nnrxd setup to rxc rising 10 ns t32 rxd hold after rxc rising 30 ns notes: 1. crs input might be asynchronous to rxc. 2. rxc starts after crs goes active. rxc stops after crs goes inactive. 3. col is an asynchronus input. w w w w w w w 7; 7;' 7;(1 5;' 5; 5;b'9 5;b(5 82 figure 23 - mii interface parameter min typ max units t27 txd0-txd3, txen100 delay from tx25 rising 0 15 ns t28 rxd0-rxd3, rx_dv, rx_er setup to rx25 rising 10 ns t29 rxd0-rxd3, rx_dv, rx_er hold after rx25 rising 10 ns 83 min nom max a4.07 a1 0.05 0.5 a2 3.17 3.67 d 30.35 30.60 30.85 d1 27.90 28.00 28.10 e3 30.35 30.60 30.85 e1 27.90 28.00 28.10 h 0.09 0.23 l 0.35 0.5 0.65 l1 1.30 e 0.50bsc o 0 o 7 o w 0.10 0.30 r1 0.20 r2 0.30 figure 24 - 208 pin qfp package outlines notes: coplanarity is 0.100 mm maximum tolerance on the position of the leads is 0.08 mm maximum package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm dimensions for foot length l when measured at the centerline of the leads are given at the table. dimension for foot length l when measured at the gauge pl ane 0.25 mm above the seating plane, is 0.6 mm details of pin 1 identifier are optional but must be located within the zone indicated 6 controlling dimension: millimeter |
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